1

2

15

16

SCLK(fCLK-CAL)

CS

Start

Power-up

Calibration

Sample

#1

tACQ

tPOWERUP-CAL

SDO

tPH_CS

tSU_CSCK

tD_CKCS

ADS7044

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SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015

Device Functional Modes (continued)

8.4.1.1 Offset Calibration on Power-Up

The device starts offset calibration on the first CS falling edge after power-up and calibration completes if the CS

pin remains low for at least 16 SCLKs after the first CS falling edge. The SDO output remains low during

calibration. The minimum acquisition time must be provided after calibration for acquiring the first sample. If the

device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up, the OCR is not

updated. Table 2 provides the timing parameters for offset calibration on power-up.

For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The

conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 37

shows the timing diagram for offset calibration on power-up.

Table 2. Offset Calibration on Power-Up

MIN

TYP

MAX

UNIT

fCLK-CAL

SCLK frequency for calibration at 2.25 V < AVDD < 3.6 V

16

MHz

fCLK-CAL

SCLK frequency for calibration at 1.65 V < AVDD < 2.25 V

12

MHz

tPOWERUP-CAL

Calibration time at power-up

16 tSCLK

ns

tACQ

Acquisition time

200

ns

tPH_CS

CS high time

tACQ

ns

Figure 37. Offset Calibration on Power-Up Timing Diagram

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