8.5 Bus Timing for DAT Signals During Dual Data Rate Operation

These timings apply to the DAT[7:0] signals only when the device is configured for dual data mode operation.

In this dual data mode, the DAT signals operate synchronously of both the rising and the falling edges of CLK.

The CMD signal still operates synchronously of the rising edge of CLK and therefore complies with the bus

timing specified in section 10.5 of JESD84-B51, therefore there is no timing change for the CMD signal.

Figure 17: Timing Diagram: Data Input/Output in Dual Data Rate Mode

Dual Data Rate Interface Timings

Table 26: High-speed Dual Data Rate Interface Timing

Parameter

Symbol

Min.

Max.

Unit

Remark

Input CLK1

Clock duty cycle

45

55

%

Includes jitter, phase

noise

Input DAT (referenced to CLK-DDR mode)

Input set-up time

tISUddr

2.5

ns

CL ≤ 20 pF

Input hold time

tIHddr

2.5

ns

CL ≤ 20 pF

Output DAT (referenced to CLK-DDR mode)

Output delay time during data transfer tODLYddr

1.5

7

ns

CL ≤ 20 pF

Signal rise time (all signals)2

tRISE

2

ns

CL ≤ 20 pF

Signal fall time (all signals)

tFALL

2

ns

CL ≤ 20 pF

Note 1: CLK timing is measured at 50% of VDD.

Note 2: Inputs CMD, DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs CMD, DAT rise and fall times are

measured by min (VOH) and max (VOL)

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