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ASFC bảng dữ liệu(PDF) 23 Page - Alliance Semiconductor Corporation |
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ASFC bảng dữ liệu(HTML) 23 Page - Alliance Semiconductor Corporation |
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23 / 42 page ![]() HS400 reference load The circuit in Figure 14 shows the reference load used to define the HS400 Device Output Timings and overshoot / undershoot parameters. The reference load is made up by the transmission line and the CREFERENCE capacitance. The reference load is not intended to be a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the reference load to system environment. Manufacturers should correlate to their production test conditions. Delay time (td) of the transmission line has been introduced to make the reference load independent from the PCB technology and trace length. Figure 14: HS400 reference load 8.3 Bus Signal Levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. Figure 15: Bus Signal Levels Open-drain Mode Bus Signal Level Table 21: Open-drain Bus Signal Level Parameter Symbol Min. Max. Unit Conditions Output HIGH voltage VOH VDD – 0.2 V IOH = -100 μA Output LOW voltage VOL 0.3 V IOL = 2 mA The input levels are identical with the push-pull mode bus signal levels. Confidential -23 /42- Rev.1.0 July 2023 32GB/64GB/128GB eMMC |
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