ADC31RF80IRMP datasheet(1/142 Pages) TI2

tên linh kiện	ADC31RF80IRMP

Giải thích chi tiết về linh kiện	ADC31RF80 3-GSPS Telecom Receiver and Feedback Device

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ADC

INP,

INM

SYSREFP,

SYSREFM

CLKINP,

CLKINM

PLL

65

Buffer

D[1:0]P,

D[1:0]M

D[3:2]P,

D[3:2]M

GPIO[4:1]

N

NCO

CTRL

SYNCBP,

SYNCBM

FOVR

NCO

ADC

Digital Block

(Interleave

Correction

Power

Detection)

Clock

Divider

SPI

and

Control

CM

N

RESET

SCLK

SDATA

SEN

PDN

SDO

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC31RF80

SBAS860 – AUGUST 2017

ADC31RF80 3-GSPS Telecom Receiver and Feedback Device

1

1 Features

1

•

14-Bit, 3-GSPS ADC

•

Noise Floor: –155 dBFS/Hz

•

RF Input Supports Up To 4.0 GHz

•

Aperture Jitter: 90 fS

•

Spectral Performance (fIN = 900 MHz, –2 dBFS):

–

SNR: 61.4 dBFS

–

SFDR: 71-dBc HD2, HD3

–

SFDR: 76-dBc Worst Spur

•

Spectral Performance (fIN = 1.85 GHz, –2 dBFS):

–

SNR: 58.5 dBFS

–

SFDR: 65-dBc HD2, HD3

–

SFDR: 75-dBc Worst Spur

•

On-Chip Digital Down-Converters:

–

Up to 2 DDCs (Dual-Band Mode)

–

Up to 3 Independent NCOs per DDC

•

On-Chip Input Clamp for Overvoltage Protection

•

Programmable On-Chip Power Detectors With

Alarm Pins for AGC Support

•

On-Chip Dither

•

On-Chip Input Termination

•

Input Full-Scale: 1.35 VPP

•

Support for Multi-Chip Synchronization

•

JESD204B Interface:

–

Subclass 1-Based Deterministic Latency

–

4 Lanes Support at 12.5 Gbps

•

Total Power Dissipation: 3.2 W at 3.0 GSPS

•

72-Pin VQFN Package (10 mm × 10 mm)

2 Applications

•

Multi-Carrier GSM Cellular Infrastructure Base

Stations

•

Telecommunications Receivers

•

DPD Observation Receivers

•

Backhaul Receivers

•

RF Repeaters and Distributed Antenna Systems

3 Description

The ADC31RF80 device is a 14-bit, 3-GSPS, single-

channel telecom receiver and feedback device that

supports RF sampling with input frequencies up to

4 GHz and beyond. Designed for high signal-to-noise

ratio (SNR), the ADC31RF80 delivers a noise

spectral density of –155 dBFS/Hz as well as dynamic

range over a large input frequency range. The

buffered

analog

input

with

on-chip

termination

provides uniform input impedance across a wide

frequency range and minimizes sample-and-hold

glitch energy.

The ADC31RF80 comes with a dual-band, digital

down-converter (DDC) with up to three independent,

16-bit numerically-controlled oscillators (NCOs) per

DDC

for

phase-coherent

frequency

hopping.

Additionally, the ADC is equipped with front-end peak

and RMS power detectors and alarm functions to

support

external

automatic

gain

control

(AGC)

algorithms.

The ADC31RF80 supports the JESD204B serial

interface with subclass 1-based deterministic latency

using data rates up to 12.5 Gbps with up to four

lanes. The device is offered in a 72-pin VQFN

package (10 mm × 10 mm) and supports the

industrial temperature range (–40°C to +85°C).

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

ADC31RF80

VQFN (72)

10.00 mm × 10.00 mm

(1) For all available packages, see the package option addendum

at the end of the data sheet.

Simplified Block Diagram

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nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Texas Instruments	ADC31RF80IRMP	8Mb / 136P	3-GSPS Telecom Receiver and Feedback Device
Texas Instruments	ADC31RF80IRMPT	8Mb / 136P	3-GSPS Telecom Receiver and Feedback Device

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