ADC31RF80IRMP datasheet(27/142 Pages) TI2

27 / 142 page

ADC

INP,

INM

SYSREFP,

SYSREFM

CLKINP,

CLKINM

PLL

Buffer

D[1:0]P,

D[1:0]M

D[3:2]P,

D[3:2]M

GPIO[4:1]

NCO

CTRL

SYNCBP,

SYNCBM

FOVR

NCO

ADC

Digital Block

(Interleave

Correction

Power

Detection)

Clock

Divider

SPI

and

Control

RESET

SCLK

SDATA

SEN

PDN

SDO

ADC31RF80

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SBAS860 – AUGUST 2017

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8 Detailed Description

8.1 Overview

The ADC31RF80 is a single-channel, 14-bit, 2949.12-MSPS, telecom receiver and feedback device containing

an analog-to-digital converter (ADC) followed by multi-band digital down-converters (DDCs), and a back-end

JESD204B digital interface.

The ADC is preceded by an input buffer and on-chip termination to provide a uniform input impedance over a

large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection

against overvoltage conditions. The ADC is internally interleaved four times and equipped with background,

analog and digital, and interleaving correction.

The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of

interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,

16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be

controlled through the SPI or GPIO pins. The ADC31RF80 also provides three different power detectors on-chip

with alarm outputs in order to support external automatic gain control (AGC) loops.

The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized,

and output on one to four lanes, depending on the ADC sampling rate and decimation. The CLKIN, SYSREF,

and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B interface

that are used to derive the internal local frame and local multiframe clocks and establish the serial link. All

features of the ADC31RF80 are configurable through the SPI.

8.2 Functional Block Diagram

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