VPUP

VTH

VTL

tW0L

Host drives SDQ

High Impedance, external pull-up

tSLOT

tREC

tF

tε

Figure 6-18. Write-Zero Timing Diagram

VPUP

VTH

VTL

tRL

Host drives SDQ

Device drives SDQ

High Impedance, external pull-up

Host Sampling Window

tREC

tSLOT

tRDS

VIH_HOST

tRC

tF

Figure 6-19. Read-Data Timing Diagram

6.5.6 IDLE

If the SDQ bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the SDQ bus

in IDLE. Bus transactions can resume at any time from the IDLE state.

6.5.7 CRC Generation

The TMF0008 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus host can compute

a CRC value from the first 56 bits of the 64-bit ROM and compare these bits to the value stored within the

TMF0008 to determine if the ROM data has been received error-free by the bus host. The equivalent polynomial

function of this CRC is: X8 + X5 + X4 +1.

The comparison of CRC values and decision to continue with an operation are determined entirely by the bus

host. No circuitry on the TMF0008 prevents a command sequence from proceeding if the CRC stored in or

TMF0008

SLVSIV3 – JULY 2025

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