8.2.1 Design Requirements

Table 8-1 summarizes the design performance goals. Table 8-2 summarizes the system design parameters.

Table 8-1. Design Goals

DESIGN GOAL

VALUE

Noise-free resolution

80,000 counts / 130,000 counts (post averaging)

Sample rate

10 SPS

Input step settling time

500 ms / 900 ms (post averaging)

50-Hz and 60-Hz noise rejection

>100 dB

Table 8-2. Design Parameters

DESIGN PARAMETERS

DESIGN VALUE

Bridge resistance

1 kΩ

Bridge excitation voltage

5 V

Load cell sensitivity

2 mV/V

Bridge full-scale output

10 mV

ADC analog power supply

5 V

Host controller and ADC digital power supply

3 V

8.2.2 Detailed Design Procedure

Common performance metrics of a weigh scale are noise-free resolution (or counts) and offset and gain stability

(drift) after calibrating the weigh scale. Table 6-1 to Table 6-4 illustrate ADC noise performance expressed as an

input-referred quantity over gain, data rate, and analog supply voltage.

In this design example, the ADC analog supply voltage (5 V) is used as the bridge excitation voltage. 5-V

excitation optimizes the bridge signal output compared to 3-V excitation and also has the benefit of optimizing

the ADC conversion noise. Gain = 128 is selected because it also provides optimal noise performance. The

front end circuitry of the ADC easily accommodates the 10-mV bridge output. In summary, the ADC configuration

that yields the highest resolution while achieving the sample rate and settling time requirements is AVDD = 5 V,

bridge excitation = 5 V, gain = 128, and sample rate = 10 SPS.

Signal-to-noise performance is improved by using a higher gauge-factor bridge (example 3 mV/V bridge), or

by increasing the excitation voltage. If the excitation voltage > 5 V, a voltage divider is required to reduce the

voltage at the ADC reference inputs.

Noise-free counts are improved by post averaging the data (for example, a moving-average filter performed in

the microcontroller). A moving average filter reduces noise by a factor of √N, where N is the number of readings

averaged. However, a moving average filter increases the input step settling time due to the latency caused by

averaging.

The other key performance attributes are DC offset and gain drift, and 50-Hz and 60-Hz noise rejection. Figure

5-14 and Figure 5-16 illustrate the distributions of offset and gain drift performance. 50-Hz and 60-Hz noise

rejection is described in Figure 7-6. The ADC provides over 100-dB rejection with ±3% variation of the ADC

clock frequency.

8.2.3 Application Curves

To evaluate the ADC's noise performance, four fixed-value, 1-kΩ low-drift precision resistors are connected in a

bridge arrangement to simulate a bridge sensor. The simulator provides the same thermal noise generated by

a physical bridge. One of the four bridge resistors is modified to 1.008 kΩ in order to provide a 10-mV output

signal. The 10-mV signal is typical of a 2-mV/V load cell using 5-V excitation.

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