7.3.8 Data Rate

The ADS123x data rate is set by the SPEED pin, as shown in Table 7-6. When SPEED is low, the data rate is

nominally 10 SPS. This data rate provides the lowest noise, and also has excellent rejection of both 50-Hz and

60-Hz line-cycle interference. For applications requiring fast data rates, setting SPEED high selects a data rate

of 80 SPS.

Table 7-6. Data Rate Settings

SPEED

PIN

DATA RATE

INTERNAL OSCILLATOR

OR 4.9152-MHz CRYSTAL

EXTERNAL

OSCILLATOR

0

10 SPS

fCLK / 491,520

1

80 SPS

fCLK / 61,440

7.3.9 Data Format

The ADS123x output 24 bits of data in binary two’s complement format. The least significant bit (LSB) has a

weight of 0.5 VREF / (223 – 1). The positive full-scale input produces an output code of 7FFFFFh and the negative

full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding

full-scale. Table 7-7 summarizes the ideal output codes for different input signals.

Table 7-7. Ideal Output Code Versus Input Signal (1)

INPUT SIGNAL VIN

(AINP – AINN)

IDEAL OUTPUT CODE

≥ 0.5 VREF / Gain

7FFFFFh

(0.5 VREF / Gain) / (223 – 1)

000001h

0

000000h

(–0.5 VREF / Gain) / (223 – 1)

FFFFFFh

≤ –0.5 VREF / Gain

800000h

(1)

Excludes effects of noise, INL, offset, and gain errors.

7.3.10 Data Ready and Data Output (DRDY/DOUT)

This digital output pin serves two purposes. First, DRDY/DOUT indicates when new data are ready by going low.

Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the

conversion data, most significant bit (MSB) first. Data are shifted out on each subsequent SCLK rising edge.

After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. DRDY/DOUT then

remains high until new data are ready. This configuration is useful when polling on the status of DRDY/DOUT to

determine when to begin data retrieval.

7.3.11 Serial Clock Input (SCLK)

This digital input shifts serial data out with each rising edge. This input has built-in hysteresis, but care must be

taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this

reason, make sure the rise-and-fall times of SCLK are less than 50 ns.

ADS1232, ADS1234

SBAS350H – JUNE 2005 – REVISED JUNE 2025

www.ti.com

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