CDx4HC164, CDx4HCT164 High-Speed CMOS Logic 8-Bit Serial-In, Parallel-Out Shift

Register

1 Features

• Buffered inputs

• Asynchronous reset

• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,

TA = 25°C

• Fanout (overtemperature range)

– Standard Outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temp range: – 55°C to 125°C

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

logic ICs

• HC types

– 2V to 6V operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC at VCC = 5V

• HCT types

– 4.5V to 5.5V operation

– Direct LSTTL input logic compatibility, VIL =

0.8V (Max), VIH = 2V (Min)

– CMOS input compatibility, II ≤ 1μA at VOL, VOH

2 Description

The ’HC164 and ’HCT164 are 8-bit, serial-in, parallel-

out, shift registers with asynchronous reset. Data is

shifted on the positive edge of Clock (CLK). A LOW

on the RESET (CLR) pin resets the shift register and

all outputs go to the LOW state regardless of the

input conditions. Two Serial Data inputs (A and B) are

provided, either one can be used as a data enable

control.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE (NOM)

CD74HC164M

SOIC (14)

8.65mm × 3.90mm

CD74HCT164M

SOIC (14)

8.65mm × 3.90mm

CD74HC164E

PDIP (14)

19.31mm × 6.35mm

CD74HCT164E

PDIP (14)

19.31mm × 6.35mm

CD54HC164F

CDIP (14)

19.55mm × 6.71mm

(1)

For all available packages, see Section 11.

Functional Block Diagram

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164

SCHS155E – NOVEMBER 1998 – REVISED MAY 2024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.