6 Detailed Description

6.1 Overview

The ’HC164 and ’HCT164 are 8-bit, serial-in, parallel-out, shift registers with asynchronous reset. Data is shifted

on the positive edge of Clock (CLK). A LOW on the RESET (CLR) pin resets the shift register and all outputs go

to the LOW state regardless of the input conditions. Two Serial Data inputs (A and B) are provided, either one

can be used as a data enable control.

6.2 Functional Block Diagram

Figure 6-1. Functional Block Diagram

6.3 Device Functional Modes

Truth Table(1)

OPERATING

MODE

INPUTS

OUTPUTS

CLR

CLK

A

B

QA

QB- QH

RESET

(CLEAR)

L

X

X

X

L

L - L

Shift

H

↑

I

I

L

qA - qF

H

↑

I

h

L

qA - qF

H

↑

h

I

L

qA - qF

H

↑

h

h

H

qA - qF

(1)

H = High voltage level.

h = High voltage level one set-up time prior to the low-to-high

clock transition.

I = Low voltage level one set-up time prior to the low-to-high

clock transition.

L = Low voltage level.

X = Don't care.

↑ = Transition from low to high level.

qn = Lower case letters indicate the state of the reference input

clock transition.

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CD54HC164, CD74HC164, CD54HCT164, CD74HCT164

SCHS155E – NOVEMBER 1998 – REVISED MAY 2024

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