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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ES9018K2M bảng dữ liệu(PDF) 40 Page - ESS Technology,Inc |
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ES9018K2M bảng dữ liệu(HTML) 40 Page - ESS Technology,Inc |
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40 / 41 page  CONFIDENTIAL Rev. 3.6 March 26, 2021 ES9018K2M Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643- 8800 • www.esstech.com 40 ORDERING INFORMATION Part Number Description Package ES9018K2M Sabre32 Reference 32-bit Low Power Stereo Audio DAC 28-pin QFN The letter K identifies the package type QFN. Revision History Rev. Date Notes 1.4 June 6, 2014 Added SABRE SOUNDTM trademark 1.5 July 22, 2014 Updated ESS Technology FAX number. Added medical use disclaimer. Emphasized that Pin 20 and the Exposed Pad must be connected to Digital Ground 1.6 August 26, 2014 Added conditions when an external DVDD regulator is required 1.7 September 8, 2014 Corrected typo on Register#7 Bit [6:5], 3’dX changed to 2’dX. Identified Left and Right channels for Registers #15 and #16 respectively. Updated DAC output impedance from 781.25 to 806 1.8 September 24, 2014 Removed reference to Right Justified data format that is not supported 1.9 October 1, 2014 Added details on the use of an external +1.3V DVDD supply 2.0 October 6, 2014 Updated Revision Identification from Chip Marking diagram. Added specification to the Absolute Maximum Ratings table 2.1 October 16, 2014 Added table to Register #65 description 2.2 December 1, 2014 Corrected value of differential current output range on page 29 2.3 January 8, 2015 Added details on decoupling required for the DVDD core supply. Deleted old revision history from 0.1 to 0.91. 2.4 March 16, 2015 Added notes on the connection of reserved Bits in the device control registers. Updated ESS contact information. 2.5 April 30, 2015 Added information on THD compensation and how to use Registers #22 to #25 2.6 June 10, 2015 Increased typical value of AVCC_L plus AVCC_R from 3mA to 8mA 2.7 July 26, 2015 Updated typical operating power on cover page. Corrected SDA setup time from SCL rising units from “µs” to “ns”. Added new specifications to the Absolute Maximum Ratings table. 2.8 April 12, 2016 Corrected typical power consumption values 2.9 January 24, 2017 Corrected THD compensation description. 3.0 January 31, 2017 Remove references to Revision W silicon, clarify I2C address description. 3.1 February 14, 2017 Added description for Registers #2, #3 and #9. Register #65 labeled as GPIO Status. Added register map. Adjusted page number references as needed. 3.2 November 28, 2017 Remove ESS logo from pin diagram 3.3 November 15, 2018 Added Low Power Audio DAC description, removed Advanced Information 3.4 April 25, 2019 Added Cin / Co / Cclk information 3.5 January 7, 2021 Updated I/V converter filter circuit 3.6 March 26, 2021 Updated Register #9 default setting |
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