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ES9018K2M bảng dữ liệu(PDF) 28 Page - ESS Technology,Inc |
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ES9018K2M bảng dữ liệu(HTML) 28 Page - ESS Technology,Inc |
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28 / 41 page ![]() CONFIDENTIAL Rev. 3.6 March 26, 2021 ES9018K2M Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643- 8800 • www.esstech.com 28 ABSOLUTE MAXIMUM RATINGS PARAMETER RATING Positive Supply Voltage (DVCC, VCCA, AVCC_L, AVCC_R) +4.7V with respect to GND Positive Supply Voltage (DVDD) +1.8V with respect to GND DAC Output voltage Range (DACL, DACR, DACLB, DACRB) GND < Vout < AVCC Storage temperature Range –65 C to +150C Operating Junction Temperature +125 C Voltage Range for Digital Input pins –0.3V to DVCC+ 0.3V ESD Protection Human Body Model (HBM) Machine Model (MM) 2000V 200V WARNING: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute –maximum–rated conditions for extended periods may affect device reliability. WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL CONDITIONS Operating temperature TA –20 C to +70C Power Supply Voltage Current nominal (Note 1) Current standby (Notes 1, 2) Digital Power Supply Voltage DVCC +1.8V 5% +3.3V 5% 13.0mA 14.2mA 0mA 0mA Internal Digital Core supply DVDD +1.2V (typical) (Note 3) External Digital Core Supply DVDD +1.3V 5% (Note 4) 50mA Analog Core Supply Voltage VCCA +3.3V 5% 0.8mA 0mA Analog Power Supply Voltage AVCC_L AVCC_R +3.3V 5% 8.0mA 0mA Total Power DVCC = +1.8V DVCC = +3.3V 52mW 76mW < 1mW < 1mW Notes: (1) fs = 44.1kHz, external MCLK = 22MHz, I2S input, DAC output connected to current-to-voltage converter, internal DVDD, all external supply voltages at nominal center values (2) With RESETB held low after setting the soft_start bit in register 14 to 1’b0 to fully ramp the DAC outputs to ground (3) Internal DVDD should be used except under the conditions described on page 7. (4) External DVDD current measured at 192kHz sample rate and MCLK = 80MHz. |
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