NB681- 28V, 6 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH 2-BIT VID

NB681 Rev. 1.04

www.MonolithicPower.com

14

12/28/2017

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Table 3—Control bit logics

LP#

C1

C0

VOUT(V)

VCCIO

0

X

X

0

1

0

0

0.85

1

0

1

0.875

1

1

0

0.95

1

1

1

0.975

VCCPRIM

_CORE

0

X

X

0.7

1

0

0

0.85

1

0

1

0.9

1

1

0

0.95

1

1

1

1.00

EDRAM/

EOPIO/

V1.0A

0

X

X

0

1

0

0

0.8 (MSM)

1

0

1

0.95

1

1

0

1

1

1

1

1.05

Others

0

X

X

0

1

0

0

1.0

1

0

1

1.075

1

1

0

1.15

1

1

1

1.2

Configuring the EN Control

EN is used to enable or disable the whole chip.

Pull EN high to turn on the regulator and pull EN

low to turn off the regulator. It is recommended to

have EN rise from 0 V to over 2.3 V in less than

1 ms.

EN works with the LP# signal to control the

output (see Table 4).

Table 4—EN/LP# control

EN

LP#

Output

PG

0

0

0 V, Off

Low

0

1

0 V, Off

Low

1

0

Normal turn on

and fall to LP#

target

value

after

PG + 1 ms

Asserted

when

output

reaches nominal voltage

and remains high during

LP# = 0

1

1

High

Remains asserted after

SS

Soft Start (SS)

The NB681 employs a soft-start (SS) mechanism

to ensure smooth output during power-up. When

EN goes high, the internal reference voltage

ramps up gradually; hence, the output voltage

ramps up smoothly as well. Once the reference

voltage reaches the target value, the soft start

finishes, and the part enters steady-state

operation.

If the output is pre-biased to a certain voltage

during start-up, the IC disables the switching of

both the high-side and low-side switches until the

voltage on the internal reference exceeds the

sensed output voltage at the internal FB node.

Power Good (PG)

The NB681 has power good (PG) output used to

indicate whether the output voltage of the buck

regulator is ready. PG is an open drain of a

MOSFET. It should be connected to 3V3 or

another voltage source through a resistor (e.g.

100 k). After the input voltage is applied, the

MOSFET is turned on so that PG is pulled to

GND before SS is ready. After the FB voltage

reaches 95 percent of VREF, PG is pulled high in

less than 10 µs. When the FB voltage drops to 90

percent of VREF (or rises higher than 115 percent

of VREF), PG is pulled low.

Note that when LP# goes from 10, PG stays

high for all the power good logic.

Start-Up and Shutdown Sequence

Figure 6 shows the start-up and shutdown

sequence including LP# and PG. To achieve a

proper start up, it is recommended to turn on EN

after VIN and VCC pass UVLO. During start-up,

PG goes high immediately when Vout reaches its

normal range. LP# mode is blanked until

PG + 1 ms, meaning the NB681 is not able to

enter LP# mode during the start-up period + 1 ms.

Vout decays to the target LPM setting when LP#

pulls low and is able to ramp up to its normal

value in the Intel required timing. PG pulls low

immediately after EN goes low.