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NB681GD bảng dữ liệu(PDF) 7 Page - Monolithic Power Systems

tên linh kiện NB681GD
Giải thích chi tiết về linh kiện  28V, 6A, Low Iq, High Current Synchronous Buck Converter with 2-Bit VID
PDF  23 Pages
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nhà sản xuất  MPS [Monolithic Power Systems]
Trang chủ  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

NB681GD bảng dữ liệu(HTML) 7 Page - Monolithic Power Systems

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NB681- 28V, 6 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH 2-BIT VID
NB681 Rev. 1.04
www.MonolithicPower.com
7
12/28/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
PIN FUNCTIONS
PIN #
Name
Description
1
VIN
Supply voltage input. The NB681 operates from a +4.5 V to +24 V input rail. An input
capacitor is needed to decouple the input rail. Use wide PCB traces and multiple vias to
make the connection with at least two layers for the input trace.
2
PGND
Power ground. Use wide PCB traces and multiple vias to make the connection.
3, 4
C1, C0
2-bit VID control input. Set C1 and C0 with MODE to get different voltage references for
different rails.
5
EN
Enable. Drive EN high to turn on the buck regulator; drive EN low to turn off the buck
regulator. EN determines USM. If EN is within 1.2 V-1.7 V, it is in USM. If EN >2.3 V, it is in
normal mode. For normal mode, it is recommended that EN rising finishes in <1 ms.
6
LP#
Low-power mode control signal. Pull LP# high in normal operation. Pull LP# low to enter
low-power mode. Usually, LP# is controlled by the SLP#S0 of the system.
7
MODE
Selection for VCCIO/PRIMCORE/EDRAM/EOPIO/V1.0 A applications with external 1%
resistors.
8
SW
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is connected to
VIN when the HS-FET is on; SW is connected to PGND when the LS-FET is on. Use wide
and short PCB traces to make the connection. SW is noisy, so keep sensitive traces away
from SW.
9
BST
Bootstrap. A >100 nF capacitor connected between SW and BST is required to form a
floating supply across the high-side switch driver.
10
3V3
External 3V3 VCC input for control and driver. Place a 1 µF decoupling capacitor close to
3V3 and AGND.
11
AGND
Signal logic ground. Make a Kelvin connection to PGND near the VCC capacitor. AGND
can be applied as a remote sense ground with proper setting.
12
VOUT
Output sense input. Connect the VOUT to the remote output capacitor with good GND
decoupling. Keep the VOUT trace away from SW or other noisy nodes. It is recommended
to use a >20 mil trace for the vout sense.
13
PG
Power good output. PG is an open-drain signal. PG is high if the output voltage is higher
than 95 percent of the nominal voltage or lower than 105 percent of the nominal voltage.



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