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TMP236A2DBZR bảng dữ liệu(PDF) 4 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TMP23x Low-Power, High-Accuracy Analog Output Temperature Sensors
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TMP235, TMP236
SBOS857E – SEPTEMBER 2017 – REVISED MAY 2019
www.ti.com
Product Folder Links: TMP235 TMP236
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply voltage, VDD
+6
V
Output voltage, VOUT
–0.3
(VDD + 0.3)
Output current
–30
+30
mA
Latch-up current, each pin
–200
+200
Junction temperature (TJ)
+150
°C
Storage temperature (Tstg)
–65
+150
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM) per JESD22-A114 (1)
±4000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Input voltage (TMP235)
2.3
5.5
V
Input voltage (TMP236)
3.1
5.5
TA
Operating free-air temperature
–40
150
°C
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2)
For information on self-heating and thermal response time see Layout Guidelines section.
(3)
The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(4)
Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.
6.4 Thermal Information
THERMAL METRIC (1)(2)
TMP235
UNIT
DCK (SC70)
DBZ (SOT-23)
PINS
PINS
RθJA
Junction-to-ambient thermal resistance(3)(4)
275
167
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
84
90
°C/W
RθJB
Junction-to-board thermal resistance
56
146
°C/W
ΨJT
Junction-to-top characterization parameter
1.2
35
°C/W
ΨJB
Junction-to-board characterization parameter
55
146
°C/W



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