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TMS320VC33 bảng dữ liệu(PDF) 35 Page - Texas Instruments

tên linh kiện TMS320VC33
Giải thích chi tiết về linh kiện  DIGITAL SIGNAL PROCESSOR
PDF  59 Pages
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TMS320VC33 bảng dữ liệu(HTML) 35 Page - Texas Instruments

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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004
35
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
switching characteristics over recommended operating conditions for XF0 when executing STFI
or STII (see Figure 23)
PARAMETER
VC33-120
VC33-150
UNIT
PARAMETER
MIN MAX
MIN MAX
UNIT
td(H3H-XF0H)
Delay time, H3 high to XF0 high†
4
3
ns
† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
XF0
Fetch
STFI or STII
Read
Execute
Decode
td(H3H-XF0H)
Figure 23. Timing for XF0 When Executing an STFI or STII



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