TFP403

TI

PanelBus™ DIGITAL RECEIVER

SLDS125B − DECEMBER 2000 − REVISED MAY 2011

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VID(2)

Differential input sensitivity†

150

1560

mVp-p

tps

Analog input intra-pair (+ to -) differential skew (see Note 6)

0.4

tbit‡

t(ccs)

Analog Input inter-pair or channel-to-channel skew

(see Note 6)

Analog Input inter-pair or channel-to-channel skew

(see Note 6)

1

tpix§

t(ijit)

Worse case differential input clock jitter tolerance¶

(see Note 6)

Worse case differential input clock jitter tolerance¶

(see Note 6)

50

ps

tf(1)

Fall time of data and control signals#, ||

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

2.4

1.9

ns

tr(1)

Rise time of data and control signals#, ||

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

2.4

1.9

ns

tr(2)

Rise time of ODCK clock#

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

2.4

1.9

ns

tf(2)

Fall time of ODCK clock#

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

2.4

1.9

ns

tsu(1)

Setup time, data, and control

signal to falling edge of ODCK

1 pixel, OCK_INV = low||,

PIXS = low

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

1.0

ns

Hold time data and control

1 pixel OCK INV = low||

ST = Low

CL = 5 pF

th(1)

Hold time, data, and control

i

l t f lli

d

f ODCK

1 pixel, OCK_INV = low||,

PIXS l

ST = Low,

CL = 5 pF

ST Hi h

C

10 F

1.0

ns

th(1)

signal to falling edge of ODCK

PIXS = low

ST = High, CL = 10 pF

1.0

ns

Setup time data and control

1 pixel OCK INV = high||

ST = Low

CL = 5 pF

tsu(2)

Setup time, data, and control

i

l t i i

d

f ODCK

1 pixel, OCK_INV = high||,

PIXS l

ST = Low,

CL = 5 pF

ST Hi h

C

10 F

1.0

ns

tsu(2)

signal to rising edge of ODCK

PIXS = low

ST = High, CL = 10 pF

1.0

ns

th(2)

Hold time, data, and control

signal to rising edge of ODCK

2 pixel and STAG

OCK_INV = high||

PIXS = high

ST = Low,

CL = 5 pF

ST = High, CL = 10 pF

0.5

ns

f

ODCK frequency

PIX = Low (1-PIX/CLK)

25

165

MHz

f(ODCK)

ODCK frequency

PIX = High (2-PIX/CLK)

12.5

82.5

MHz

ODCK duty-cycle

40%

50%

60%

tpd(PDL)

Propagation delay time from PD low to Hi-Z outputs

9

ns

tpd(PDOL)

Propagation delay time from PDO low to Hi-Z outputs

9

ns

tt(HSC)

Transition time between DE transition to SCDT lowk

1e6

tpix

tt(FSC)

Transition time between DE transition to SCDT highk

1600

tpix

td

Delay time, ODCK latching edge to QE[23:0] data output

STAG = Low

Pixs = High

0.5

tpix

† Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.

‡ tbit is 1/10 the pixel time, tpix

§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in

2-pixel/clock mode.

¶ Measured differentially at 50% crossing using ODCK output clock as trigger.

# Rise and fall times measured as time between 20% and 80% of signal amplitude.

|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]

kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.

NOTE 6: By characterization