3

Device

SN74LVC3G17

SCES470F – AUGUST 2003 – REVISED AUGUST 2015

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC3G17 device contains three buffers and performs the Boolean function Y = A. The device functions

as three independent buffers, but because of Schmitt action, it may have different input threshold levels for

positive-going (VT+) and negative-going (VT–) signals. In this application, the engineer chooses to use just a

single Schmitt Trigger buffer. In this case, the other two inputs should be tied to VCC or GND.

9.2 Typical Application

Figure 4. Device Power Button Circuit

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus

contention because it can drive currents that would exceed maximum limits. Outputs can be combined to

produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions

should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

–

For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.

–

Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.

2. Recommend Output Conditions:

–

Load currents should not exceed 50 mA per output and 100 mA total for the part.

–

Series resistors on the output may be used if the user desires to slow the output edge signal or limit the

output current.

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