SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2)

PARAMETER

TEST CONDITIONS

SN54LS173A

SN74LS173A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

fmax

Maximum clock frequency

30

50

30

50

MHz

tPHL

Propagation delay time,

high-to-low-level output from clear input

26

35

26

35

ns

tPLH

Propagation delay time,

low-to-high-level output from clock input

CL = 45 pF

17

25

17

25

ns

tPHL

Propagation delay time,

high-to-low-level output from clock input

L

22

30

22

30

ns

tPZH

Output enable time to high level

15

23

15

23

ns

tPZL

Output enable time to low level

18

27

18

27

ns

tPHZ

Output disable time from high level

CL =5 pF

11

20

11

20

ns

tPLZ

Output disable time from low level

CL = 5 pF

11

17

11

17

ns