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SN65MLVD206B bảng dữ liệu(PDF) 21 Page - Texas Instruments

tên linh kiện SN65MLVD206B
Giải thích chi tiết về linh kiện  SN65MLVD206B Multipoint-LVDS Line Driver and Receiver (Transceiver) With IEC ESD Protection
PDF  38 Pages
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nhà sản xuất  TI2 [Texas Instruments]
Trang chủ  https://www.ti.com
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SN65MLVD206B bảng dữ liệu(HTML) 21 Page - Texas Instruments

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Type 1
Transition Regions
Type 2
Low
High
Low
High
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SN65MLVD206B
www.ti.com
SLLSEX9A – DECEMBER 2016 – REVISED FEBRUARY 2020
Product Folder Links: SN65MLVD206B
Submit Documentation Feedback
Copyright © 2016–2020, Texas Instruments Incorporated
9.2.3.5 Termination Resistors
As shown earlier, an M-LVDS communication channel employs a current source driving a transmission line which
is terminated with two resistive loads. These loads serve to convert the transmitted current into a voltage at the
receiver input. To ensure good signal integrity, the termination resistors should be matched to the characteristic
impedance of the transmission line. The designer should ensure that the termination resistors are within 10% of
the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the
termination resistors should be between 90 Ω and 110 Ω. The line termination resistors are typically placed at the
ends of the transmission line.
9.2.3.6 Receiver Input Signal
The M-LVDS receivers herein comply with the M-LVDS standard and correctly determine the bus state. These
devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential voltage
over the common mode range of –1 V to 3.4 V.
9.2.3.7 Receiver Input Threshold (Failsafe)
The MLVDS standard defines a Type-1 and Type-2 receiver. Type-1 receivers have their differential input voltage
thresholds near zero volts. Type-2 receivers have their differential input voltage thresholds offset from 0 V to
detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in
Table 5 and Figure 18.
Table 5. Receiver Input Voltage Threshold Requirements
RECEIVER TYPE
OUTPUT LOW
OUTPUT HIGH
Type 1
–2.4 V
≤ VID ≤ –0.05 V
0.05 V
≤ VID ≤ 2.4 V
Type 2
–2.4 V
≤ VID ≤ 0.05 V
0.15 V
≤ VID ≤ 2.4 V
Figure 18. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region
9.2.3.8 Receiver Output Signal
Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V
to 3.6 V.
9.2.3.9 Interconnecting Media
The physical communication channel between the driver and the receiver may be any balanced paired metal
conductors meeting the requirements of the M-LVDS standard, the key points which will be included here. This
media may be a twisted pair, twinax, flat ribbon cable, or PCB traces.
The nominal characteristic impedance of the interconnect should be between 100 Ω and 120 Ω with variation no
more than 10% (90 Ω to 132 Ω).



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