1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VDD1

SCKO2

SCKO3

DGND1

FS1

FS2

SR

VCC

AGND

XT1

VDD3

SCKO1

SCKO0

DGND3

DGND2

MCKO2

MCKO1

VDD2

CSEL

XT2

DBQ PACKAGE

(TOP VIEW)

PLL1707-Q1

SLES259A

– JUNE 2010 – REVISED MARCH 2011

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AGND

9

-

Analog ground

CSEL

12

I

SCKO1 frequency selection control(1)

DGND1

4

-

Digital ground 1

DGND2

16

-

Digital ground 2

DGND3

17

-

Digital ground 3

FS1

5

I

Sampling frequency group control 1(1)

FS2

6

I

Sampling frequency group control 2(1)

MCKO1

14

O

27-MHz master clock output 1

MCKO2

15

O

27-MHz master clock output 2

SCKO0

18

O

System clock output 0 (33.8688 MHz fixed)

SCKO1

19

O

System clock output 1 (selectable for 48 kHz)

SCKO2

2

O

System clock output 2 (256 fS selectable)

SCKO3

3

O

System clock output 3 (384 fS selectable)

SR

7

I

Sampling rate control(1)

VCC

8

-

Analog power supply, 3.3 V

VDD1

1

-

Digital power supply 1, 3.3 V

VDD2

13

-

Digital power supply 2, 3.3 V

VDD3

20

-

Digital power supply 3, 3.3 V

XT1

10

I

27-MHz crystal oscillator, or external clock input

XT2

11

O

27-MHz crystal oscillator, must be OPEN for external clock input mode

4

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Product Folder Link(s): PLL1707-Q1