PLL1707-Q1

SLES259A

– JUNE 2010 – REVISED MARCH 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

TA

PACKAGE(2)

ORDERABLE PART NUMBER

TOP-SIDE MARKING

-40

°C to 85°C

SSOP - DBQ

Reel of 2500

PLL1707IDBQRQ1

PLL1707I

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VCC

Supply voltage: VDD1-VDD3

4 V

ΔVCC

Supply voltage differences: VDD1-VDD3

±0.1 V

Ground voltage differences: AGND, DGND1-DGND3

±0.1 V

VI

Digital input voltage: FS1, FS2, SR, CSEL

-0.3 V to (VDD + 0.3) V

VI

Analog input voltage, XT1, XT2

-0.3 V to (VCC + 0.3) V

II

Input current (any pins except supplies)

±10 mA

TA

Ambient temperature range

-40

°C to 85°C

Tstg

Storage temperature

-55

°C to 150°C

TJ

Junction temperature

150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

TA = 25°C, VDD1-VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT/OUTPUT

Logic input

CMOS compatible

VIH

0.7 VDD

3.6

Input logic level(1)

Vdc

VIL

0.3 VDD

IIH

VIN = VDD

65

100

Input logic current(1)

µA

IIL

VIN = 0 V

±10

Logic output

CMOS

VOH

IOH = -4 mA

VDD - 0.4

Vdc

Output logic level(2)(3)

VOL

IOL = 4 mA

0.4

Vdc

Standard fS

32

44.1

48

Sampling frequency

kHz

Double fS

64

88.2

96

(1)

Pins 5, 6, 7, 12: FS1, FS2, SR, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)

(2)

Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1

(3)

Not production tested

2

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Product Folder Link(s): PLL1707-Q1