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PCM1802DB bảng dữ liệu(PDF) 25 Page - Texas Instruments |
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PCM1802DB bảng dữ liệu(HTML) 25 Page - Texas Instruments |
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25 / 35 page ![]() 3 4 5 6 7 20 19 18 17 16 15 14 10 F + 3.3V 5V It is recommended to place a top layer ground pour for shielding around PCM1802 and connect to lower main PCB ground plane by multiple vias VINL VINR VREF1 VREF2 VCC AGND PDWN MODE1 MODE0 FMT1 FMT0 OSR SCKI VDD PCM1802 Clock signals to DSP or Audio Processor 1 2 Top Layer Ground Pour Top Layer Signal Traces Via to bottom Ground Plane Pad to top layer ground pour 0.1 F 1 F 1 F R-ch IN L-ch IN Control Option External RC antialiasing circuit Make sure to have ground pour separating the Left and Right channel traces to help prevent crosstalk Make sure to have ground pour separating the clock signals from surrounding traces 8 9 10 13 12 11 BYPAS TEST LRCK DGND DOUT BCK 10 F + 0.1 F Control Bypass Capacitors are 0.1 uF and 10 uF 25 PCM1802 www.ti.com SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016 Product Folder Links: PCM1802 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated 10.2 Layout Example Figure 30. Layout Recommendation |
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