SLAS787 datasheet(10/52 Pages) TI2

10 / 52 page

MSP430G2231-Q1

SLAS787B – NOVEMBER 2011 – REVISED MARCH 2014

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8.5 Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend

rw:

Bit can be read and written.

rw-0,1:

Bit can be read and written. It is reset or set by PUC.

rw-(0,1):

Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address

00h

ACCVIE

NMIIE

OFIE

WDTIE

rw-0

WDTIE

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

interval timer mode.

OFIE

Oscillator fault interrupt enable

NMIIE

(Non)maskable interrupt enable

ACCVIE

Flash access violation interrupt enable

Address

01h

Table 7. Interrupt Flag Register 1 and 2

Address

02h

NMIIFG

RSTIFG

PORIFG

OFIFG

WDTIFG

rw-0

rw-(0)

rw-(1)

rw-1

rw-(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault.

PORIFG

Power-On Reset interrupt flag. Set on VCC power-up.

RSTIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.

NMIIFG

Set via RST/NMI pin

Address

03h

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