LP3954TLXSLASHNOPB datasheet(34/58 Pages) TI2

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SDA

SCL

START condition

STO

P condition

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP3954

SNVS340D – JUNE 2005 – REVISED MARCH 2013

www.ti.com

Limit(1)

Symbol

Parameter

Unit

Min

Max

Enable Lag Time

Clock Low Time

Clock High Time

Data Setup Time

Data Hold Time

Data Access Time

Disable Time

Data Valid

Data Hold Time

I2C COMPATIBLE INTERFACE

I2C Signals

In I2C mode the LP3954 pin SCK is used for the I2C clock SCL and the pin SS is used for the I2C data signal

SDA. Both these signals need a pull-up resistor according to I2C specification. SI pin is the address select pin.

I2C address for LP3954 is 54h when SI = 0 and 55h when SI = 1. Unused pin SO can be left unconnected.

I2C Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

Figure 38. I2C Signals: Data Validity

I2C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

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