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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS3103ADBTR bảng dữ liệu(PDF) 49 Page - Texas Instruments |
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TAS3103ADBTR bảng dữ liệu(HTML) 49 Page - Texas Instruments |
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49 / 152 page  2−15 Table 2−2. Sample Rate and CLK Ratios Sample Rate DAP Cycles MCLK RATIO Sample Rate DAP Cycles Req’d 768 512 384 256 192 128 PLL[1:0] = 00 96 134,400 135.168 88.1 123,340 124.0448 48 67,200 135.168 101.376 67.584 44.1 61,740 124.1856 93.1392 62.0928 32 44,800 135.168 90.112 67.584 45.056 24 33,600 135.168 101.376 67.584 50.688 33.792 22.1 30,940 124.4672 93.3504 62.2336 46.6752 31.1168 8 11,200 67.584 45.056 33.792 22.528 16.896 PLL[1:0] = 01 96 134,400 135.168 88.1 123,340 124.0448 48 67,200 135.168 101.376 67.584 44.1 61,740 124.4672 93.1392 62.0928 32 44,800 135.168 90.112 67.584 45.056 24 33,600 101.376 67.584 50.688 33.792 22.1 30,940 93.3504 62.2336 46.6752 31.1168 8 11,200 33.792 22.528 16.896 PLL[1:0] = 10 96 134,400 88.1 123,340 48 67,200 67.584 44.1 61,740 62.0928 32 44,800 67.584 45.056 24 33,600 50.688 33.792 22.1 30,940 46.6752 31.1168 8 11,200 16.896 11.264 2.2.1 TAS3103A Sample-Rate Changes The TAS3103A supports dynamic sample rate changes when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the TAS3103A remains in normal operation and the register contents are preserved. To avoid producing audio artifacts during sample-rate changes, the volume or mute control may be included in the application firmware that can mute the output signal during the sample-rate change. The fixed-frequency clock can be provided by a crystal attached to XTLI and XTLO, or an external fixed-frequency master clock attached to MCLKI. When the TAS3103A is used in a system in which the master clock frequency can change, then any time MCLK is stopped or the frequency is changed, reset should be applied. If the system master clock frequency changes or stops, reset should be applied. In these cases, the following procedures should be used (see Figure 2−14). |
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