DAC8581

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SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012

THEORY OF OPERATION

The DAC8581 uses a proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data are

coded in twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface

sends the input data to the DAC latch. The digital data are then decoded to select a tap voltage of the resistor

string. The resistor string output is sent to a high-performance output amplifier. The output buffer has bipolar (±5

V) swing capability on a 600-

Ω, 200-pF load. The resistor string DAC architecture provides exceptional

differential linearity and temperature stability whereas the output buffer provides fast-settling, low-glitch, and

exceptionally low idle-channel noise. The DAC8581 settles within 1

μs for large input signals. Exceptionally low

glitch (0.5 nV-s) is attainable for small-signal, code-to-code output changes. The resistor string architecture also

provides code-independent power consumption and code-independent settling time. The DAC8581 resistor string

needs an external reference voltage to set the output voltage range of the DAC. To aid fast settling, VREF input is

internally buffered.

Supply Pins

The DAC8581 uses ±5-V analog power supplies (AVDD, AVSS) and a 1.8-V to 5.5-V digital supply (DVDD). Analog

and digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power

and ground pins should be separated. Sufficient bypass capacitors, at least 1

μF, should be placed between

AVDD and AVSS, AVSS and DGND, and DVDD and DGND pins. Series inductors are not recommended on the

supply paths. The digital input pins should not exceed the ground potential during power up. During power up,

AGND and DGND are first applied with all digital inputs and the reference input kept at 0 V. Then, AVDD, DVDD,

AVSS, and VREF should be applied together. Care should be taken to avoid applying VREF before AVDD and AVSS.

All digital pins must be kept at ground potential before power up.

Reference Input Voltage

The reference input pin VREF is typically tied to a +3.3-V, +4.096-V, or +5.0-V external reference. A bypass

capacitor (0.1

μF or less) is recommended, depending on the load-driving capability of the voltage reference. To

reduce crosstalk and improve settling time, the VREF pin is internally buffered by a high-performance amplifier.

The VREF pin has constant 5-kΩ impedance to AGND. The output range of the DAC8581 is equal to ±VREF

voltage. The VREF pin should be powered at the same time, or after the supply pins. REF3133 and REF3140 are

recommended to set the DAC8581 output range to ±3.3 V and ±4.096 V, respectively.

Output Voltage

The input data format is in twos-complement format as shown in Table 1. The DAC8581 uses a high-

performance, bipolar output buffer capable of driving a 600-

Ω, 200-pF load with fast 0.65-μs settling. The buffer

has exceptional noise performance (20 nV/

√Hz) and fast slew rate (35 V/μs). The small-signal settling time is

under 300 ns, allowing update rates up to 3 MSPS. Loads of 50

Ω or 75 Ω could be driven as long as output

current does not exceed ±25 mA continuously. Long cables, up to 1 nF in capacitance, can be driven without the

use of external buffers. To aid stability under large capacitive loads (>1 nF), a small series resistor can be used

at the output.

Table 1. Data Format

DIGITAL CODE

DAC OUTPUT

BINARY

HEX

+VREF

0111111111111111

7FFF

+VREF/2

0100000000000000

4000

0

0000000000000000

0000

–VREF/2

1011111111111111

BFFF

–VREF

1000000000000000

8000

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