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AFE4403 bảng dữ liệu(PDF) 24 Page - Texas Instruments |
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AFE4403 bảng dữ liệu(HTML) 24 Page - Texas Instruments |
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24 / 85 page ![]() LED2 SLED2 t1 CONVLED2 ADCRST0 t2 t3 t4 t5 24 AFE4404 SBAS689D – JUNE 2015 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: AFE4404 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) Refers to one clock period of CLK_TE. (2) See Figure 36 for notations of the clocking domain. (3) tADC = 1 / fADC. 8.3.6.3 Receiver Timing The timing engine can be programmed to set the different phases of the receiver. The relative timings of the LED phase, sampling phase, ADC reset phase, and ADC conversion phases are shown in Figure 33 and Table 7. Figure 33. Receiver Timing Guidelines Table 7. Receiver Timing Details MIN MAX UNIT t1 Start of LED to start of sampling Max [25, (0.2 × LED pulse duration)] µs t2 End of LED to start of ADC reset phase 2 Counts(1) t3 Duration of ADC reset phase 6 Counts t4 End of ADC reset phase to start of ADC conversion phase 2 2 Count t5 Duration of ADC conversion phase(2) (NUMAV + 2) × 200 × tADC + 15 (3) µs |
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