TMP116 datasheet(19/46 Pages) TI2

19 / 46 page

I/O

Control

Interface

SCL

SDA

Temperature

Configuration

LOW

EEPROM1 to 4

Pointer

HIGH

TMP116, TMP116N

www.ti.com

SBOS740A – MAY 2017 – REVISED MAY 2019

Product Folder Links: TMP116

Submit Documentation Feedback

Programming (continued)

7.5.2 Pointer Register

Figure 26 shows the internal register structure of the TMP116. The 8-bit pointer register of the device is used to

address a given data register. The power-up reset value is 00. By default, the TMP116 reads the temperature on

power-up.

Figure 26. Internal Registers Structures

7.5.3 I2C and SMBus Interface

7.5.3.1 Serial Interface

The TMP116 operates as a slave device on the two-wire, SMBus and I2C interface-compatible bus. Connections

to the bus are made through the open-drain I/O lines SDA and SCL pins. The SDA and SCL pins feature

integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise.

The device supports the transmission protocol for fast (1 kHz to 400 kHz) mode. Register bytes are sent with the

most significant byte first, followed by the least significant byte.

7.5.3.1.1

Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus is controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high-

to low-logic level when the SCL pin is high. All slaves on the bus shift in the slave address byte on the rising

edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock

pulse, the slave being addressed responds to the master by generating an acknowledge and pulling the SDA pin

low.

A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data

transfer, the SDA pin must remain stable when the SCL pin is high because any change in the SDA pin when the

SCL pin is high is interpreted as a START or STOP signal.

When all data are transferred, the master generates a repeated START or STOP condition. The STOP condition

is indicated by pulling the SDA pin from low to high when the SCL pin is high.

TMP116 bảng dữ liệu(PDF) 19 Page - Texas Instruments

TMP116 bảng dữ liệu(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL