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ST72321B bảng dữ liệu(PDF) 30 Page - STMicroelectronics

tên linh kiện ST72321B
Giải thích chi tiết về linh kiện  64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST72321B bảng dữ liệu(HTML) 30 Page - STMicroelectronics

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
of the comparator output. This means it is generat-
ed when either one of these two events occur:
–VEVD rises up to VIT+(EVD)
–VEVD falls down to VIT-(EVD)
The EVD function is illustrated in Figure 18.
For more details, refer to the Electrical Character-
istics section.
Figure 18. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generate an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
VEVD
VIT+(EVD)
VIT-(EVD)
AVDF
0
0
1
IF AVDIE = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
Mode
Description
WAIT
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
HALT
The SICSR register is frozen.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
AVD event
AVDF
AVDIE
Yes
No



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