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M65KG256AB bảng dữ liệu(PDF) 41 Page - STMicroelectronics

tên linh kiện M65KG256AB
Giải thích chi tiết về linh kiện  256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PDF  51 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KG256AB bảng dữ liệu(HTML) 41 Page - STMicroelectronics

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Figure 20.
Read followed by Write using the Burst Read Terminate Command (BST)
1.
If the Write operation is performed to the same bank and row than the Read operation, the Burst Read Terminate command
(BST) must be issued to terminate the Read operation.The WRIT command can then be issued tBSTW (ŠtBSTW) after the
BST command.
2.
If the Write operation is performed to the same bank but to a different row, the bank must be precharged to interrupt the
Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD
after the ACT command.
3.
If the Write operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4.
If the Write operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
Command
K
K
DO1
UDQS,
LDQS
DQ0-DQ15
READ
BST
NOP
t0
t1
t2
t3
t4
t5
tBSTZ (
≥tBSTZ)
DO0
ai11209
t6
t7
t8
WRIT
NOP
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
UDQM,
LDQM
DI0 DI1 DI2 DI3
tBSTZ ( = CL)
Data Output
Data Input



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