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ADS5281IPFPR bảng dữ liệu(PDF) 28 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  12-Bit Octal-Channel ADC Family Up to 65MSPS
PDF  41 Pages
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ADS5281IPFPR bảng dữ liệu(HTML) 28 Page - Texas Instruments

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95
85
80
75
70
60
ClockDutyCycle(%)
35
65
50
45
40
55
SNR(dBFS)
SFDR(dBc)
f =65MHz
f
=10MHz
S
IN
90
60
65
95
85
80
75
70
60
ClockDutyCycle(%)
20
80
50
40
30
60
SNR(dBFS)
SFDR(dBc)
f =65MHz
f
=10MHz
S
IN
90
70
65
10
-
10
-
30
-
50
-
70
-
90
-
110
-
130
-
150
InputFrequency(MHz)
0
2
20
18
16
14
12
10
8
6
4
f =65MHz
f =10MHz( 7dBFS)
f =16.1MHz( 7dBFS)
IMD= 97dBFS
-
-
-
S
1
2
60
40
30
20
10
0
CodeBin(LSB)
2049
2052
2051
2050
2053
50
2054
f =65MSPS
S
0%
0%
0.37%
0.28%
51.92%
47.43%
0.5
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.5
Code(LSB)
0
4096
3072
2048
2560
1536
3584
1024
512
-
0.4
-
0.3
f =50MSPS
f
=5MHz
S
IN
0.35
0.25
0.15
0.05
-
0.05
-
0.15
-
0.35
Code(LSB)
0
4096
3072
2048
2560
1536
3584
1024
512
-
0.25
f =50MSPS
f
=5MHz
S
IN
ADS5281
ADS5282
SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%
clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input
common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer
current setting = 3.5mA, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC
DISABLED
ENABLED
Figure 22.
Figure 23.
HISTOGRAM OF OUTPUT CODE FOR ZERO INPUT
INTERMODULATION DISTORTION
Figure 24.
Figure 25.
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
Figure 26.
Figure 27.
28
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5281 ADS5282



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