ADS5281IPFPR datasheet(22/41 Pages) TI

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CLOCK, REFERENCE, AND DATA OUTPUT MODES

INPUT CLOCK

EXTERNAL REFERENCE

VREF =1.5V+

1.5V

(1)

VREF =1.5V

1.5V

(2)

ADS5281

ADS5282

SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

NAME

DIFF_CLK

EN_DCC

EXT_REF_VCM

PHASE_DDR<1:0>

BTC_MODE

MSB_FIRST

EN_SDR

FALL_SDR

The ADS528x is configured by default to operate with a single-ended input clock—CLKP is driven by a CMOS

clock and CLKN is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a

differential input clock on CLKP and CLKN. Operating with a low-jitter differential clock usually gives better SNR

performance, especially at input frequencies greater than 30MHz.

In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable

an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.

The ADS528x can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,

the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have

enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The

advantage of using the external reference mode is that multiple ADS528x units can be made to operate with the

same external reference, thereby improving parameters such as gain matching across devices. However, in

applications that do not have an available high drive, differential external reference, the ADS528x can still be

driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the

INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFT and REFB are

generated as shown in Equation 1 and Equation 2.

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