PCM1796DBR datasheet(39/63 Pages) TI2

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PCM1796

SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006

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Audio Format

The PCM1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,

and 24-bit audio data, as shown in Figure 40. The audio format is selected by the FMT[2:0] bits of control register18.

MSB

LSB

BCK

DATA,

DATAL, DATAR

1/4 fS or 1/8 fS

WDCK

Audio Data Word = 16-Bit

Audio Data Word = 20-Bit

Audio Data Word = 24-Bit

9 10 11 12 13 14 15

MSB

LSB

9 10 11 12 13 14 15

17 18 19

MSB

LSB

9 10 11 12 13 14 15

17 18 19

21 22 23

DATA,

DATAL, DATAR

DATA,

DATAL, DATAR

Figure 40. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application

System Clock (SCK) and Interface Timing

The PCM1796 in an application using an external digital filter requires the synchronization of WDCK and the system

clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL,

and DATAR is shown in Figure 41.

DATA

DATAL

DATAR

t(BCH)

BCK

WDCK

t(BCL)

t(LB)

t(BCY)

t(DS)

t(DH)

1.4 V

t(BL)

1.4 V

PARAMETER

MIN

MAX

UNITS

t(BCY) BCK pulse cycle time

t(BCL) BCK pulse duration, LOW

t(BCH) BCK pulse duration, HIGH

t(BL)

BCK rising edge to WDCK falling edge

t(LB)

WDCK falling edge to BCK rising edge

t(DS)

DATA, DATAL, DATAR setup time

t(DH)

DATA, DATAL, DATAR hold time

Figure 41. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application

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