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PCM1796DBR bảng dữ liệu(PDF) 24 Page - Texas Instruments

tên linh kiện PCM1796DBR
Giải thích chi tiết về linh kiện  24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER
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PCM1796DBR bảng dữ liệu(HTML) 24 Page - Texas Instruments

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PCM1796
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
www.ti.com
24
TIMING DIAGRAM
SDA
SCL
t(BUF)
t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD)
t(SCL-F)
t(SCL-R)
t(HI)
Repeated Start
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R)
t(P-SU)
Stop
t(SP)
TIMING CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
MAX
UNIT
f(SCL)
SCL clock frequency
Standard
100
kHz
f(SCL)
SCL clock frequency
Fast
400
kHz
t(BUF)
Bus free time between stop and start conditions
Standard
4.7
µs
t(BUF)
Bus free time between stop and start conditions
Fast
1.3
µs
t(LOW)
Low period of the SCL clock
Standard
4.7
µs
t(LOW)
Low period of the SCL clock
Fast
1.3
µs
t(HI)
High period of the SCL clock
Standard
4
µs
t(HI)
High period of the SCL clock
Fast
600
ns
t(RS-SU)
Setup time for (repeated) start condition
Standard
4.7
µs
t(RS-SU)
Setup time for (repeated) start condition
Fast
600
ns
t(S-HD)
Hold time for (repeated) start condition
Standard
4
µs
t(RS-HD)
Hold time for (repeated) start condition
Fast
600
ns
t(D-SU)
Data setup time
Standard
250
ns
t(D-SU)
Data setup time
Fast
100
ns
t(D-HD)
Data hold time
Standard
0
900
ns
t(D-HD)
Data hold time
Fast
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-R)
Rise time of SCL signal
Fast
20 + 0.1 CB
300
ns
t(SCL-R1)
Rise time of SCL signal after a repeated start condition and after an
Standard
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated start condition and after an
acknowledge bit
Fast
20 + 0.1 CB
300
ns
t(SCL-F)
Fall time of SCL signal
Standard
20 + 0.1 CB
1000
ns
t(SCL-F)
Fall time of SCL signal
Fast
20 + 0.1 CB
300
ns
t(SDA-R)
Rise time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Fast
20 + 0.1 CB
300
ns
t(SDA-F)
Fall time of SDA signal
Standard
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Fast
20 + 0.1 CB
300
ns
t(P-SU)
Setup time for stop condition
Standard
4
µs
t(P-SU)
Setup time for stop condition
Fast
600
ns
C(B)
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
Fast
50
ns
VNH
Noise margin at high level for each connected device (including hysteresis)
0.2 VDD
V
Figure 34. Timing Definition on the I2C Bus



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