PCM1792DB datasheet(20/62 Pages) TI2

20 / 62 page

PCM1792

SLES069B − MARCH 2003 − REVISED NOVEMBER 2006

www.ti.com

FUNCTION DESCRIPTIONS

Zero Detect

The PCM1792 has a zero-detect function. When the PCM1792 detects the zero conditions as shown in Table 2, the

PCM1792 sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH.

Table 2. Zero Conditions

MODE

DETECTING CONDITION AND TIME

PCM

DATA is continuously LOW for 1024 LRCKs.

External DF Mode

DATA is continuously LOW for 1024 WDCKs.

DSD

DZ0

There are and equal number of 1s and 0s in every 8 bits of DSD

input data for 200 ms.

DSD

DZ1

The input data is 1001 0110 continuously for 200 ms.

Serial Control Interface

The PCM1792 supports SPI and I2C that sets mode control registers as shown in Table 4. This serial control interface

is selected by MSEL (pin 3); SPI is activated when MSEL is set to LOW, and I2C is activated when MSEL is set to

HIGH.

SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and

the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The

control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10). MDO is the serial data output,

used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;

MC is the serial bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used

to enable the internal mode register access.

All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word

format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For

read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or

address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to,

or the data that was read from, the register specified by IDX[6:0].

Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1

state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen

clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data

on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on

MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the

indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.

PCM1792DB bảng dữ liệu(PDF) 20 Page - Texas Instruments

PCM1792DB bảng dữ liệu(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

bảng dữ liệu tải về

Link URL