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LP8720 bảng dữ liệu(PDF) 16 Page - Texas Instruments

tên linh kiện LP8720
Giải thích chi tiết về linh kiện  LP8720 One Step-Down DC-DC and Five Linear Regulators with I2C-Compatible Interface
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LP8720 bảng dữ liệu(HTML) 16 Page - Texas Instruments

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LP8720
SNVS575B – JULY 2008 – REVISED MAY 2013
www.ti.com
D-Type and LO-Type LDO Electrical Characteristics (continued)
Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10
µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, TJ= -40 to +125°C
(1)
Limit
Parameter
Test Conditions
LDO#
Typ
Units
Min
Max
PSRR
Power Supply Ripple
f =10 kHz, COUT = 1 µF, IOUT = 20
1,4,5
55
dB
Rejection Ratio
mA(3)
tstartup
Startup Time from Shutdown
COUT = 1 µF, IOUT = IMAX
(3)
1,4,5
35
µs
VTransient
Startup Transient Overshoot
COUT = 1µF, IOUT = IMAX
(3)
1,4,5
30
mV
COUT
External output capacitance
1,4,5
1.0
0.5
20
µF
for stability
Serial Interface
Unless otherwise noted, VVBATT = VVINB = VVIN1 = VVIN2 = 3.6V, GND = GNDB = 0V, CVBATT = CVIN1 = CVIN2 = 2.2 µF, CVINB = 10
µF. Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the
entire junction temperature range for operation, TJ= -40 to +125°C
(1) (2)
Limit
Unit
Parameter
Test Conditions
Typ
s
Min
Max
fCLK
Clock Frequency
400
kHz
tBF
Bus-Free Time between START and STOP
1.3
µs
tHOLD
Hold Time Repeated START Condition
0.6
µs
tCLK-LP
CLK Low Period
1.3
µs
tCLK-HP
CLK High Period
0.6
µs
tSU
Set-Up Time Repeated START Condition
0.6
µs
tDATA-HOLD
Data Hold Time
50
ns
tDATA-SU
Data Set-Up Time
100
ns
tSU
Set-Up Time for STOP Condition
0.6
µs
tTRANS
Maximum Pulse Width of Spikes that Must Be Suppressed by
50
ns
the Input Filter of Both DATA and CLK Signals
(1)
All limits are specified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
(2)
Ensured by design.
16
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LP8720



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