ωPOLE

ω

AO

LG

*

=

1 + j

(j )

ω

1 + j

(ESR x C

ω

L)

1 + j

((ESR + R

ω

O // RL) CL)

RO

VREF

CL

RL

LOOP

GAIN

+

-

13

LP3982

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SNVS185F – FEBRUARY 2002 – REVISED APRIL 2017

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Ceramic capacitor of the value required by the LP3982 are available in the following dielectric types: Z5U, Y5V,

X5R, and X7R. The Z5U and Y5V types exhibit a 50% or more drop in capacitance value as their temperature

increases from 25°C, an important consideration. The X5R generally maintain their capacitance value within

±20%. The X7R type are desirable for their tighter tolerance of 10% over temperature.

Ceramic capacitors pose a challenge because of their relatively low ESR. Like most other LDOs, the LP3982

relies on a zero in the frequency response to compensate against excessive phase shift in the feedback loop of

the regulator. If the phase shift reaches 360° (that is, becomes positive), the regulator oscillates. This

compensation usually resides in the zero generated by the combination of the output capacitor with its ESR. The

zero is intended to cancel the effects of the pole generated by the load capacitance (CL) combined with the

parallel combination of the load resistance (RL) and the output resistance (RO) of the regulator. The challenge

posed by low ESR capacitors is that the zero it generates can be too high in frequency for the pole it is intended

to compensate. The LP3982 overcomes this challenge by internally generating a strategically placed zero.

Figure 16. Simplified Model of Regulator Loop Gain Components

Figure 16 shows a basic model for the linear regulator that helps describe what happens to the output signal as it

is processed through its feedback loop; that is, describe its loop gain (LG). The LG includes two main transfer

functions: the error amplifier and the load. The error amplifier provides voltage gain and a dominant pole, while

the load provides a zero and a pole. The LG of the model in Figure 16 is described by Equation 7:

(7)

The first term of Equation 7 expresses the voltage gain (numerator) and a single pole role-off (denominator) of

the error amplifier. The second term expresses the zero (numerator) and pole (denominator) of the load in

combination with the RO of the regulator.

Figure 17 shows a Bode plot that represents a case where the zero contributed by the load is too high to cancel

the effect of the pole contributed by the load and RO. The solid line represents the loop gain while the dashed

line represents the corresponding phase shift. Notice that the phase shift at unity gain is a total 360°, the criteria

for oscillation.