LM3556

SNVS796D – AUGUST 2011 – REVISED OCTOBER 2015

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Feature Description (continued)

Additionally, the IVM-D threshold sets the input voltage boundary that forces the LM3556 to either stop ramping

the flash current during start-up (Stop and Hold Mode) or to start decreasing the LED current during the flash

(Adjust Down Only Mode and Adjust Down and Up Mode). The IVM-U threshold sets the input voltage boundary

that forces the LM3556 to start ramping the flash current back up towards the target (Adjust Up and Down

Mode). The IVM-U threshold is equal to the IVM-D value plus the programmed hysteresis value also stored in the

Input Voltage Flash Monitor (IVFM) Mode Register (0x01).

To help prevent a premature current reduction, the LM3556 has four different filter timers that start once the input

voltage decreases below the IVM-D line. These filter times are set in the Silicon Revision and Filter Time

Register (0x00). For more information, refer to Input Voltage Flash Monitor (IVFM) Mode Register (0x01) and

Configuration Register (0x07).

7.3.3 Fault Protections

7.3.3.1 Fault Operation

Upon entering a fault condition, the LM3556 sets the appropriate flag in the Flags Register (0x0B), placing the

part into standby by clearing and locking the Torch Enable bit (TEN), Pre-Charge bit, and Mode bits (M1, M0) in

the Enable Register (0x0A), until the Flags Register (0x0B) is read back via I2C.

7.3.3.2 Flash Time-Out

The Flash time-out period sets the amount of time that the flash current is being sourced from the current source

(LED). The LM3556 has 8 time-out levels ranging 100 ms to 800 ms in 100-ms steps. The flash time-out period

is controlled in the Flash Features Register (0x08). Flash time-out only applies to the Flash Mode operation. The

mode bits are cleared upon a flash time-out.

7.3.3.3 Overvoltage Protection (OVP)

The output voltage is limited to typically 5 V (see VOVP in Electrical Characteristics . In situations such as an open

LED, the LM3556 device raises the output voltage in order to keep the LED current at its target value. When

VOUT reaches 5 V (typical), the overvoltage comparator trips and turns off the internal NFET. When VOUT falls

below the VOVP off threshold, the LM3556 begins switching again. The mode bits in the Enable Register (0x0A)

are not cleared upon an OVP.

7.3.3.4 Current Limit

The LM3556 features selectable inductor-current limits that are programmable through the Flash Features

Register (0x08) of the I2C-compatible interface. When the inductor-current limit is reached, the LM3556

terminates the charging phase of the switching cycle.

Because the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the

device operates in Pass Mode. In Boost Mode or Pass Mode, if VOUT falls below 2.3 V, the device stops

switching, and the PFET operates as a current source limiting the current to 200 mA. This prevents damage to

the LM3556 and excessive current draw from the battery during output short-circuit conditions. The mode bits in

the Enable Register (0x0A) are not cleared upon a current limit event.

Pulling additional current from the VOUT node during normal operation is not recommended.

7.3.3.5 NTC Thermistor Input (TEMP)

The TEMP pin serves as a threshold detector for negative temperature coefficient (NTC) thermistors. It interrupts

the LED current when the voltage at TEMP goes below the programmed threshold. The NTC threshold voltage is

adjustable from 200 mV to 900 mV in 100-mV steps. The NTC current is adjustable from 25 µA to 100 µA in 25-

µA steps. When an overtemperature event is detected, the LM3556 can be set to force the LED current from

Flash Mode into Torch Mode or into shutdown. These settings are adjusted via the NTC Settings Register (0x02),

and the NTC detection circuitry can be enabled or disabled via the Enable Register (0x0A). If enabled, the NTC

block turns on and off during the start and stop of a flash, torch, or indicator event. The NTC mode of operation is

set by adjusting the NTC Mode bit in the Configuration Register (0x07). See NTC Settings Register (0x02) for

more details. The mode bits in the Enable Register (0x0A) are cleared upon an NTC event.

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