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LM34910CSDX/NOPB bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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LM34910CSDX/NOPB bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 21 page ![]() LM34910C SNVS517B – MAY 2007 – REVISED MARCH 2013 www.ti.com PC BOARD LAYOUT The LM34910C regulation, over-voltage, and current limit comparators are very fast, and respond to short duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be as neat and compact as possible, and all of the components must be as close as possible to their associated pins. The current loop formed by D1, L1, C2 and the SGND and ISEN pins should be as small as possible. The ground connection from C2 to C1 should be as short and direct as possible. If it is expected that the internal dissipation of the LM34910C will produce excessive junction temperatures during normal operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad on the bottom of the IC package can be soldered to a ground plane, and that plane should extend out from beneath the IC, and be connected to ground plane on the board’s other side with several vias, to help dissipate the heat. The exposed pad is internally connected to the IC substrate. Additionally the use of wide PC board traces, where possible, can help conduct heat away from the IC. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperatures. 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM34910C |
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