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WM8994ECS/R bảng dữ liệu(PDF) 283 Page - Cirrus Logic |
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WM8994ECS/R bảng dữ liệu(HTML) 283 Page - Cirrus Logic |
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283 / 363 page ![]() WM8994 Rev 4.6 283 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R513 (0201h) AIF1 Clocking (2) 5:3 AIF1DAC_DIV [2:0] 000 Selects the AIF1 input path sample rate relative to the AIF1 output path sample rate. This field should only be changed from default in modes where the AIF1 input path sample rate is slower than the AIF1 output path sample rate. 000 = Divide by 1 001 = Divide by 1.5 010 = Divide by 2 011 = Divide by 3 100 = Divide by 4 101 = Divide by 5.5 110 = Divide by 6 111 = Reserved 2:0 AIF1ADC_DIV [2:0] 000 Selects the AIF1 output path sample rate relative to the AIF1 input path sample rate. This field should only be changed from default in modes where the AIF1 output path sample rate is slower than the AIF1 input path sample rate. 000 = Divide by 1 001 = Divide by 1.5 010 = Divide by 2 011 = Divide by 3 100 = Divide by 4 101 = Divide by 5.5 110 = Divide by 6 111 = Reserved Register 0201h AIF1 Clocking (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R516 (0204h) AIF2 Clocking (1) 4:3 AIF2CLK_SRC [1:0] 00 AIF2CLK Source Select 00 = MCLK1 01 = MCLK2 10 = FLL1 11 = FLL2 2 AIF2CLK_INV 0 AIF2CLK Invert 0 = AIF2CLK not inverted 1 = AIF2CLK inverted 1 AIF2CLK_DIV 0 AIF2CLK Divider 0 = AIF2CLK 1 = AIF2CLK / 2 0 AIF2CLK_ENA 0 AIF2CLK Enable 0 = Disabled 1 = Enabled Register 0204h AIF2 Clocking (1) |
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