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WM8994ECS/R bảng dữ liệu(PDF) 71 Page - Cirrus Logic

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Giải thích chi tiết về linh kiện  Multi-channel Audio Hub CODEC for Smartphones
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nhà sản xuất  CIRRUS [Cirrus Logic]
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WM8994
Rev 4.6
71
“Digital Audio Interface Control”. See “General Purpose Input/Output” to configure the GPIO1 pin as
ADCLRCLK1. The ADCLRCLK1
rate is controlled as described in “Digital Audio Interface Control”.
When
ultrasonic mode is enabled, the audio band filtering and digital volume controls (see “Digital
Volume and Filter Control
”) are bypassed on the affected output paths.
The Dynamic Range Control (DRC) function is not available on the AIF1 output signal paths in
ultrasonic mode. Note, however, that the DRC is still available on the AIF input paths in this case.
The ultrasonic (4FS) signal paths are illustrated in Figure 23. The AIF1ADC_4FS register bit is defined
in Table 21.
AIF1ADC_4FS
DIGITAL AUDIO
INTERFACE 1 (AIF1)
+
+
+
+
0R
0L
1R
1L
0R
0L
1R
1L
Left / Right source select / Mono Mix control
AIF1 Slot 1
AIF1 Slot 0
AIF1 Slot 1
AIF1 Slot 0
fs / 4fs Select
DRC
DRC
EQ
3D
3D
EQ
DRC
DRC
Figure 23 Ultrasonic (4FS) Signal Paths
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1040 (0410h)
AIF1 ADC1
Filters
15
AIF1ADC_4FS
0
Enable AIF1ADC ultrasonic mode
(4FS) output, bypassing all AIF1
baseband output filtering
0 = Disabled
1 = Enabled
Table 21 Ultrasonic (4FS) Mode Control



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