WM8994ECSSLASHR datasheet(200/363 Pages) CIRRUS

200 / 363 page

WM8994

200

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1568

(0620h)

Oversampling

ADC_OSR128

ADC / Digital Microphone Oversample

Rate Select

0 = Low Power

1 = High Performance

DAC_OSR128

DAC Oversample Rate Select

0 = Low Power

1 = High Performance

R1824

(0720h)

Pull Control

(1)

MCLK1_PU

MCLK1 Pull-up enable

0 = Disabled

1 = Enabled

MCLK1_PD

MCLK1 Pull-down enable

0 = Disabled

1 = Enabled

Table 109 System Clocking

BCLK AND LRCLK CONTROL

The digital audio interfaces (AIF1 and AIF2) use BCLK and LRCLK signals for synchronisation. In

master mode, these are output signals, generated by the WM8994. In slave mode, these are input

signals to the WM8994. It is also possible to support mixed master/slave operation.

The BCLK and LRCLK signals are controlled as illustrated in Figure 69

. See the “Digital Audio

Interface Control

” section for further details of the relevant control registers.

AIF1CLK

AIF1_BCLK_DIV [4:0]

f/N

BCLK1

LRCLK1

AIF1DAC_RATE [10:0]

f/N

ADCLRCLK1/

GPIO1

AIF1ADC_RATE [10:0]

MASTER

MODE

CLOCK

OUTPUTS

AIF2_BCLK_DIV [4:0]

f/N

GPIO3/

BCLK2

GPIO4/

LRCLK2

AIF2DAC_RATE [10:0]

f/N

GPIO6/

ADCLRCLK2

AIF2ADC_RATE [10:0]

AIF2_MSTR

AIF1_MSTR

AIF2CLK

MASTER

MODE

CLOCK

OUTPUTS

f/N

Figure 69 BCLK and LRCLK Control

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