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CDCS504TPWRQ1 bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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CDCS504TPWRQ1 bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 18 page ![]() 1 IN 8 VDD 2 GND 7 OE 3 GND 6 OUT 4 GND 5 FS Not to scale 3 CDCS504-Q1 www.ti.com SCAS951 – APRIL 2017 Product Folder Links: CDCS504-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Pin Configuration and Functions PW Package 8-Pin TSSOP Top View Pin Functions PIN TYPE DESCRIPTION NAME NO. FS 5 I Frequency multiplication selection, internal pullup GND 2, 3, 4 Ground Ground IN 1 I LVCMOS clock input OE 7 I Output enable, internal pullup OUT 6 O LVCMOS clock output VDD 8 Power 3.3-V power supply (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Supply voltage –0.5 4.6 V VIN Input voltage –0.5 4.6 V Vout Output voltage –0.5 4.6 V IIN Input current (VI < 0, VI > VDD) 20 mA Iout Continuous output current 50 mA TJ Maximum junction temperature 125 °C Tstg Storage temperature –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1500 V Charged-device model (CDM), per AEC Q100-011 ±750 |
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