F0448 Datasheet

X0008129 Rev.1.4

Feb 17, 2021

Page 28

tS

tH

tP

tCH

tCL

CLK

DATA

CSb

tL

tLS

tLC

tL

Figure 70. Serial Timing Diagram

Table 7. SPI Timing Diagram Values for Figure 70

Parameter

Symbol

Test Condition

Minimum

Typical

Maximum

Unit

CLK Frequency

fC

10

MHz

CLK High Duration Time

tCH

50

ns

CLK Low Duration Time

tCL

50

ns

DATA to CLK Setup Time

tS

10

ns

CLK Period [a]

tP

100

ns

CLK to DATA Hold Time

tH

10

ns

CSb to CLK Setup Time

tLS

10

ns

CSb Trigger Pulse Width

tL

10

ns

CSb Trigger to CLK Setup Time [b]

tLC

10

ns

[a] (tCH + tCL) ≥ 1/fC

[b] Once all desired DATA is clocked in, tLC represents the time a CSb high needs to occur before any subsequent CLK signals.