ADS5413

SLWS153 − DECEMBER 2003

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2

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE/ORDERING INFORMATION(1)

PRODUCT

PACKAGE LEAD

PACKAGE

DESIGNATOR

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

ADS5413

HTQFP-48(2)

PowerPAD

PHP

−40

°C to 85°C

AZ5413

ADS5413IPHP

Tray, 250

(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.

(2) Thermal pad size: 3,5 mm

× 3,5 mm

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

UNITS

AVDD measured with respect to AGND

−0.3 V to 3.9 V

Supply voltage range

OVDD measure with respect to OGND

−0.3 V to 3.9 V

Digital input, measured with respect to AGND

−0.3 V to AVDD + 0.3 V

Reference inputs Vrefb or Vreft, measured with respect to AGND

−0.3 V to AVDD + 0.3 V

Analog inputs Vinp or Vinn, measured with respect to AGND

−0.3 V to AVDD + 0.3 V

Maximum storage temperature

150

°C

Soldering reflow temperature

235

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS(1)

MIN

NOM

MAX

UNIT

ENVIRONMENTAL

Operating free-air temperature, TA

−40

85

°C

SUPPLIES

Analog supply voltage, V(AVDD)

3

3.3

3.6

V

Output driver supply voltage, V(OVDD)

1.6

3.6

V

ANALOG INPUTS

Input common-mode voltage

CML(2)

V

Differential input voltage range

2

VPP

CLOCK INPUTS, CLK AND CLKC

Sample rate, fS = 1/tc

5

65

MHz

Differential input swing (see Figure 17)

1

6

VPP

Differential input common-mode voltage (see Figure 18)

1.65

V

Clock pulse width high, tw(H) (see Figure 16, with DCA off)

6.92

ns

Clock pulse width low, tw(L) (see Figure 16, with DCA off)

6.92

ns

(1) Recommended by design and characterization but not tested at final production unless specified under the electrical characteristics section.

(2) See V(CML) in the internal reference generator section.