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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

clkena Signals

The Cyclone III device family supports clkena signals at the GCLK network level.

This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the

output clock, the PLL does not need a resynchronization or re-lock period because the

circuit gates off the clock at the clock network level. In addition, the PLL can remain

locked independent of the clkena signals because the loop-related counters are not

affected.

Figure 5–4 shows how to implement the clkena signal.

1 The clkena circuitry controlling the output C0 of the PLL to an output pin is

implemented with two registers instead of a single register, as shown in Figure 5–4.

Figure 5–5 shows the waveform example for a clock output enable. The clkena signal

is sampled on the falling edge of the clock (clkin).

1 This feature is useful for applications that require low power or sleep mode.

The clkena signal can also disable clock outputs if the system is not tolerant to

frequency overshoot during PLL resynchronization.

Figure 5–4. clkena Implementation

clkena

clkena_out

clk_out

clkin

Figure 5–5. clkena Implementation: Output Enable

clkin

clkena

clk_out

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