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Bosch Sensortec | BMA456 Data Sheet

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Modifications reserved | Data subject to change without notice

Document number: BST-BMA456-DS000-08

Revision_3.5_032025

Primary Interface I2C/SPI Protocol Selection

The protocol is automatically selected based on the chip select CSB pin behavior after power-up.

At reset / power-up, BMA456 is in I2C mode. If CSB is connected to VDDIO during power-up and not

changed, the sensor interface works in I2C mode. For using I2C, it is recommended to hard-wire the

CSB line to VDDIO. Since power-on-reset is only executed when, both VDD and VDDIO are

established, there is no risk of incorrect protocol detection due to power-up sequence.

If CSB sees a rising edge after power-up, the BMA456 interface switches to SPI until a reset or the

next power-up occurs. Therefore, a CSB rising edge is needed before starting the SPI communication.

Hence, it is recommended to perform a SPI single read of register CHIP_ID (the obtained value will be

invalid) before the actual communication start, in order to use the SPI interface.

If toggling of the CSB bit is not possible without data communication, there is in addition the spi_en bit

in Register NV_CONF, which can be used to permanently set the primary interface to SPI without the

need to toggle the CSB pin at every power-up or reset.

SPI interface and protocol

The timing specification for SPI of the BMA456 is given in the following table:

SPI timing, valid at VDDIO ≥ 1.71V

Parameter

Symbol

Condition

Min

Max

Units

Clock Frequency

fSPI

Max. Load on SDI

or SDO = 30pF,

VDDIO ≥ 1.62 V

MHz

VDDIO < 1.62V

MHz

SCK Low Pulse

tSCKL

VDDIO>=1.62V

SCK High Pulse

tSCKH

VDDIO>=1.62V

SCK Low Pulse

tSCKL

VDDIO<1.62V

SCK High Pulse

tSCKH

VDDIO<1.62V

SDI Setup Time

tSDI_setup

SDI Hold Time

tSDI_hold

SDO Output Delay

tSDO_OD

Load = 30pF, VDDIO

≥ 1.62V

CSB Setup Time

tCSB_setup

CSB Hold Time

tCSB_hold

Idle time between write

accesses, suspend

mode, low-power mode 1

tIDLE_wacc_sum

450

µs

Idle time after write and

read access, active state

tIDLE_wr_act

µs

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