AD4080BBCZ datasheet(10/94 Pages) AD

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Data Sheet

AD4080

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 10 of 94

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Type1

Description

power off and both VDD11and IOVDD must be connected with an external voltage

source within their allowed specification limits.

If VDDLDO is connected to a voltage source, neither VDD11 nor IOVDD should be

connected to any external voltage source.

B4, B5

DCO−, DCO+

LVDS Echo Clock Outputs.

In LVDS data interface mode (default), this pin pair outputs a buffered and delayed

version of CLK+ and CLK−. Data outputs from LVDS Data Lane DA+ and Data Lane

DA− (and Data Lane DB+ and Data Lane DB− if active) are clocked out in alignment

with both rising and falling edges of DCO+ and DCO−. In SPI data interface mode (or

if the echo clock mode is disabled while in LVDS data interface mode), these pins can

be left unconnected.

IOGND

Digital Interface Supply Ground Reference. This pin must be connected to the same

ground plane as all other GND pins.

All pins specified as type DI, DO, or DI/O must use this ground reference.

CLK+/DCLK

Data Interface Clock Input Multifunction Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data

clock input, and an external 100 Ω termination resistor must be present between it and

the CLK− pin.

In SPI data interface mode, the single-ended data clock signal must be applied to this

pin.

C3 to C5, D3 to D5,

E3 to E5

GND

Grounds. All ground pins must be connected to a PCB GND plane.

DB+/SDOC

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB− serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output C (SDOC), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

falling edge of the data interface clock (DCLK).

This pin must left unconnected if not being used.

DA+/SDOA

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA− serves as the

primary LVDS Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output A (SDOA), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

falling edge of the data interface clock (DCLK).

This pin must left unconnected if not being used.

IN+

Positive Analog Differential Input.

AUXIN+

Positive Auxiliary Analog Differential Input.

DB−/SDOD

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB+ serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output D (SDOD), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

falling edge of the data interface clock (DCLK). Note that this pin does not go into a

high impedance state when used in four-lane SPI mode when CS is inactive.

This pin must be left unconnected if not being used.

DA−/SDOB

Data Interface Output

In LVDS data interface mode (default), this output pin along with DA+ serves as the

primary LVDS Data Lane A. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output B (SDOB). This is

the only active serial data output in single lane mode. Result data is shifted out of this

pin on the falling edge of the data interface clock (DCLK).

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