AD4080BBCZ datasheet(79/94 Pages) AD

79 / 94 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. A | 79 of 94

Stream Mode Register

Address: 0x0E, Reset: 0x00, Name: STREAM_MODE

This mode is not supported.

Figure 120. Stream Mode Register

Table 43. Bit Descriptions for STREAM_MODE

Bits

Bit Name

Description

Reset

Access

[7:0]

LOOP_COUNT

Stream Mode Loop Counter. These bits set the data byte count before looping to the start address. When streaming

data, a nonzero value sets the number of data bytes written before the address loops back to the start address.

A maximum of 255 bytes can be written using this approach. A value of 0x00 disables the loop back so that

addressing wraps around at the upper and lower limits of the memory. After writing to this register, the loop value

applies only to the next SPI instruction and auto clears upon the end of that instruction.

0x0

R/W

Transfer Configuration Register

Address: 0x0F, Reset: 0x00, Name: TRANSFER_CONFIG

This register controls how data moves between the controller and the target registers.

Figure 121. Transfer Configuration Register

Table 44. Bit Descriptions for TRANSFER_CONFIG

Bits

Bit Name

Description

Reset

Access

[7:3]

RESERVED

Reserved. Write 0b00000 to these bits.

0x0

KEEP_STREAM_LENGTH_VAL

Keep Stream Length. When set, the loop counter does not reset on the CS rising edge.

0x0

R/W

[1:0]

RESERVED

Reserved. Write 0b00 to these bits.

0x0

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